In semiconductor memory devices, there has been adopted an arrangement in which a redundant area for redundant cells is provided separate from a memory area for normal cells. The semiconductor memory device in which a defective cell has been detected is remedied by replacing the defective cell (fail cell) with a redundant cell based upon fail information obtained by conducting a wafer test, etc. By way of example, the correspondence between the address of a fail cell and a redundant address is set based upon whether or not a fuse is blown. If a memory cell to be accessed is a fail cell, the replacement of which with a redundant cell has been made, the redundant cell that is selected by a redundant address is accessed in place of the fail cell.
The unit of the replacement of a fail cell with a redundant cell (termed redundant replacement) has become smaller in recent years (e.g., redundant replacement is now performed in units of single word lines and 2-bit line pairs, etc.). As a result, in a case where the influence of physical data of an adjacent word line or adjacent bit line should be taken into account in a device that has a fail cell replaced with a redundant cell, the importance of a test that writes and reads certain physical data over the entirety of the chip is growing. For example, in a dynamic memory in which one cell comprises one transistor and one capacitor, after data that sets the terminal voltage of the cell capacitor to a high potential (also referred to as “cell-high data”) has been written to the memory, the data of this cell is read out and compared with an expected value.
In this case, when a redundant word line or redundant bit line is accessed in a device which has a fail cell remedied by replacing the fail cell with a redundant cell, the number of the redundant line that is selected cannot be determined and which logical data has been read out cannot be determined. This can cause problems.
An expected-value comparing-type parallel test has been proposed heretofore in order to improve the rate of fail-bit detection and improve testability. With an ordinary parallel test, items of data that have been read out of a memory cell are compared with each other. The expected-value comparing-type parallel test, however, compares the data with expected-value data that has been written to a register.
In this specification, the term “parallel test” refers to a test mode in which a plurality of memory cells are tested at one time on a selected word line, although there is no particular limitation. The scope of the parallel test spans a plurality of columns, e.g., 16 I/O bits [the 16 columns are 4-bit data in each of four banks in the case of DDR (Double Data Rate)].
As an example of an expected-value comparing-type parallel test, Patent Document 1 discloses an arrangement having a holding circuit for holding write data to a memory cell of a memory array, the write data from the holding circuit being written to the memory cell of a selected address; a comparator to which the data read out of the memory cell is input and to which the data held in the holding circuit is input as expected-value data, an non-inverted value or inverted value of the write data held in the holding circuit being output as write data to the memory cell and expected-value data to the comparator in accordance with the value of an inversion control signal; and a discriminating circuit for outputting an error flag based upon a match detection signal connected to a plurality of the comparators.
[Patent Document 1] Japanese Patent Kokai Publication No. JP-P2004-310918A
The following analysis is given by the present invention. The disclosure of the above-mentioned Patent Document 1 is herein incorporated by reference thereto.
A problem with the expected-value comparing-type parallel test is that the expected value is unknown in a case where the target of the test is an I/O bus of an ordinary memory array that is not a redundant cell. For example, in a case where a certain value is selected as an X address (row address) and reading is performed upon successively scanning column addresses in an amount of, e.g., eight columns (e.g., “LLHHLLHH”, where “H” represents high and “L” represents low) after cell-high data has been written in its entirety, and in a case where another value is selected as an X address and reading is performed upon successively scanning column addresses in an amount of, e.g., eight columns (e.g., “HLLHHLLH”), the patterns of the read data values will be different from each other. That is, when a memory cell is replaced with a redundant cell, what number redundant word line and redundant bit line used as the replacement line is arbitrarily determined. Consequently, the expected values of a plurality of memory cells to which cell-high data has been written will be unknown. In an expected-value comparing-type parallel test, therefore, if parallel data relating to separate X addresses is compared with the same expected value, a “fail” result will be obtained and the test cannot be conducted normally.